| 摘要 |
A semiconductor device and a layout method of a decoupling capacitor thereof are disclosed. The semiconductor device includes a main power/ground voltage voltage supplying line arranged in a first direction; a plurality of decoupling capacitor cells to reduce power noise generated by the power voltage and the ground voltage in the first direction and in a second direction; a plurality of sub power voltage supplying lines arranged in the second direction in a border of the plurality of decoupling capacitor cells; and a plurality of sub ground voltage supplying lines arranged in a net form in the border of the plurality of decoupling capacitor cells, wherein the plurality of decoupling capacitor cells have a first active region arranged to receive the ground voltage and the second active region disposed to receive the power voltage and to avoid a region where an inversion is formed in the decoupling capacitor.
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