发明名称 FAILURE VERIFICATION METHOD, FAILURE VERIFICATION DEVICE AND FAILURE VERIFICATION PROGRAM FOR LOGIC SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To provide a technique for efficiently finding out a failure occurrence condition in verification of a black box of a logic system comprising hardware and software. <P>SOLUTION: The verification device for clarifying the failure occurrence condition acquires each combination failure occurrence probability index and a verified combination failure occurrence integrated value for verified test items of the logic system, further acquires a combination failure occurrence integrated value of each unverified test item of the logic system, and extracts an unverified test item in which the unverified test item combination failure occurrence integrated value is closest to a value obtained by multiplying the verified combination failure occurrence integrated value by a certain ratio factor as the next verification object. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008197962(A) 申请公布日期 2008.08.28
申请号 JP20070033246 申请日期 2007.02.14
申请人 FUJITSU LTD 发明人 TADA TOSHIHIKO
分类号 G06F11/22;G06F11/28 主分类号 G06F11/22
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