| 摘要 |
A control apparatus programs, reads, and erases trapped charges representing multiple data bits from a charge trapping region of a NMOS dual-sided charge-trapping nonvolatile memory cell includes a programming circuit, an erasing circuit, and a reading circuit. The programming circuit provides a negative medium large program voltage to cell's gate along with positive drain and source voltage to inject hot carriers of holes to two charge trapping regions, one of a plurality of threshold adjustment voltages representing a portion of the multiple data bits to the drain and source regions to set the hot carrier charge levels to the two charge trapping regions. The erasing circuit provides a very large positive erase voltage to tunnel the electrons from cell's channel to whole trapping layer including the two charge trapping regions. The reading circuit generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages representative of multiple data bits, generates a drain voltage level to activate the charge-trapping nonvolatile memory cell.
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