SYSTEM AND METHOD FOR ON-CHIP IM3 REDUCTION OVER A BROAD RANGE OF OPERATING POWERS
摘要
Sets of power amplifier branches are power combined within each amplifier stage and each set of branches are biased in different classes of operation by bias circuits possessing different impedance characteristics such that the fundamental frequency components present at the output are in-phase with one another and the IMD3 components are anti-phase over a range of power levels. The RF input signal is provided by the output of the previous stage, each stage being formed by power combining sets of power amplifier branches each separately biased so the fundamental components are additive, while the IM3 components cancel partially or completely. Using a feed forward control loop to monitor the input power and appropriately adjusting the bias currents and impedance characteristics of the bias circuits feeding the individual branches can provide additional IM3 reduction or cancellation over a large range of output powers.
申请公布号
WO2008043098(A3)
申请公布日期
2008.08.28
申请号
WO2007US80699
申请日期
2007.10.08
申请人
KRISHNAMURTHY, VIKRAM BIDARE;KHANIJOUN, TANVEER KAUR;HERSHBERGER, KYLE MARK
发明人
KRISHNAMURTHY, VIKRAM BIDARE;KHANIJOUN, TANVEER KAUR;HERSHBERGER, KYLE MARK