| 摘要 |
The invention relates to an integrated circuit comprising a plurality of processing modules ( 21, 23, M, S; IP) and a network (NoC) arranged for coupling processing modules ( 21, 23, M, S; IP), comprising: the processing module ( 21, 23, M, S; IP) includes an associated network interface (NI) which is provided for transmitting data to the network (NoC) supplied by the associated processing module and for receiving data from the network (NoC) destined for the associated processing module; wherein the data transmission between processing modules ( 21, 23, M, S; IP) operates based on time division multiple access (TDMA) using time slots; each network interface (NI) includes a slot table for storing an allocation of a time slot to a connection (C 1 -C 4 ), wherein multiple connections (C 1 -C 4 ) are provided between a first processing module ( 21, M, IP) and a second processing module ( 23, S, IP) and a sharing of time slots allocated to these multiple connections between the first and a second processing modules is provided. The invention use the idea to utilize all or a part of time slots in common, which are allocated for multiple connections between a first and a second processing module, in order to reduce the latency of such connections. By sharing of slots assigned to multiple connections between two processing module a large pool of slots during one revolution of a slot table is formed. Thus the latency to access a burst of data could be reduced.
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