| 摘要 |
Capacitive coupling between adjacent parallel lines in an integrated circuit is made more uniform and allows for better timing control of the lines through the use of inverters placed on one or both of the adjacent interconnect lines. By staggering the placement of inverters along adjacent lines, constructive and destructive coupling terms between the lines are balanced out. The propagation delay through the inverter is made less than the propagation delay through one half of the line length of the corresponding line.
|
