发明名称 Method of connecting substrates of a vertically integrated circuit structure
摘要 <p>A top substrate (1) is partitioned into a first subpart (13) with a metallizing structure and a second silicon subpart (14) with a circuit structure. The metallizing structure contains metal strips (3) and source (4), gate (5) and drain (6) transistor connectors fitted contiguously on the silicon subpart corresponding to a transistor structure.</p>
申请公布号 EP1128433(B1) 申请公布日期 2008.06.18
申请号 EP20010104042 申请日期 2001.02.20
申请人 GIESECKE & DEVRIENT GMBH 发明人 GRASSL, THOMAS, DR.
分类号 H01L23/48;H01L21/768 主分类号 H01L23/48
代理机构 代理人
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