| 摘要 |
A semiconductor memory device is provided to improve write margin time even in case of writing in a cell with large storage contact resistance by advancing enable time of a column cell selection signal, by outputting a not-delayed column address pulse signal during write operation. A column address control unit(80) outputs a column address pulse signal operating a column during burst period by receiving a read/write command signal outputted from a command decoder, and outputs the column address pulse signal at timing more delayed rather than in case of receiving the write command signal, in case of receiving the read command signal. A column decoding unit(120) outputs a column cell selection signal by decoding a column address according to the output of the column address control unit. A sense amplifier(130) senses and amplifies voltage difference between a bit line and a bit bar line in response to the column cell selection signal.
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