| 发明名称 |
Design method for semiconductor integrated circuit |
| 摘要 |
In a standard cell in which an active area and a gate conductor are provided, the active area has a largest length in a gate width direction at an end thereof in a gate length direction.
|
| 申请公布号 |
US2007111405(A1) |
申请公布日期 |
2007.05.17 |
| 申请号 |
US20060518199 |
申请日期 |
2006.09.11 |
| 申请人 |
WATANABE SHINJI;YAMASHITA KYOJI;OOTANI KATSUHIRO |
发明人 |
WATANABE SHINJI;YAMASHITA KYOJI;OOTANI KATSUHIRO |
| 分类号 |
H01L21/8232;H01L21/335 |
主分类号 |
H01L21/8232 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
