| 摘要 |
A process for manufacturing a non-volatile memory cell including a floating gate MOS transistor, including the steps of: forming a gate dielectric over a surface of a semiconductor material layer; forming a conductive floating gate electrode insulated from the semiconductor material layer by the gate dielectric; forming at least one isolation region laterally to the floating gate electrode; excavating the at least one isolation region; filling the excavated isolation region with a conductive material; and forming a conductive control gate electrode of the floating gate MOS transistor insulatively over the floating gate, wherein the step of forming the floating gate electrode includes: laterally aligning the floating gate electrode to the at least one isolation region; and the step of excavating includes: lowering an isolation region exposed surface below a floating gate electrode exposed surface, the lowering exposing walls of the floating gate electrode; forming a protective layer on exposed walls of the floating gate electrode; and etching the at least one isolation region essentially down to the gate dielectric, the protective layer protecting against etching a portion of the at least one isolation region near the gate dielectric.
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