发明名称 Design of low inductance embedded capacitor layer connections
摘要 The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.
申请公布号 US2007108552(A1) 申请公布日期 2007.05.17
申请号 US20060516377 申请日期 2006.09.06
申请人 WAN LIXI 发明人 WAN LIXI
分类号 H01L29/00 主分类号 H01L29/00
代理机构 代理人
主权项
地址