| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumption by improving the power recovery rate of a PDP drive unit. SOLUTION: An output buffer circuit 10 is constituted of a totem pole circuit obtained by cascade-connecting two Nch MOS transistors Q1, Q2, and a node (VOUT) of the two MOS transistors Q1, Q2 is connected to a data electrode C0 of a display cell. A level shift circuit 11 is constituted of a CMOS circuit and drives the output buffer circuit 10. A charge recovery circuit 13 is connected to a power supply VDD2 of the output buffer circuit 10 to recover and reuse charge existing in the data electrode C0 after discharging the display cell. A power supply control circuit 12 controls the power supply voltage of the level shift circuit 11 so as to exceed the sum of the power supply voltage of the output buffer circuit 10 and the threshold voltage of the MOS transistors in a partial period of a recovery/reuse cycle in the charge recovery circuit 13. COPYRIGHT: (C)2007,JPO&INPIT
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