发明名称 Method and Apparatus for Testing Logic Circuit Designs
摘要 Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.
申请公布号 US2007113129(A1) 申请公布日期 2007.05.17
申请号 US20060538245 申请日期 2006.10.03
申请人 NEC LABORATORIES AMERICA, INC. 发明人 BALAKRISHNAN KEDARNATH;WANG SEONGMOON;WEI WENLONG;CHAKRADHAR SRIMAT T.
分类号 G01R31/28;G06F11/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址