| 摘要 |
PROBLEM TO BE SOLVED: To reduce an array occupancy area of ferroelectric memory. SOLUTION: Two ferroelectric memory cells (MC) are arranged for every three word lines (WL0-WL5) in the row direction, and two ferroelectric memory cells are arranged for every three bit lines (BL0-BL5) in the column direction. The memory cells are arranged so that the arrangement patterns are shifted by one bit in adjacent rows, and the arrangement patterns are shifted by one bit also in adjacent columns. A bit line pair is selected so that one bit memory cell is connected to the bit pair according to the position of a selected memory cell. The memory cells can be arranged in high density and the array occupancy area can be reduced accordingly. COPYRIGHT: (C)2007,JPO&INPIT
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