发明名称 Method and apparatus for supporting verification, and computer product
摘要 In gates, a gate length is same as that of an isolated Poly on a layout, however, is different from that of the isolated Poly on an actual silicon wafer. When the distance between the gates that is spacing between the gate becomes larger to some degree, the proximity effect is lost and the proximity Poly becomes same as the isolated Poly. In this way, because the correlation with another macro-cell arranged adjacent differs when the distance between the gates differs, the correlation coefficient varies. Therefore, correlation is grouped according to the distance between the gates.
申请公布号 US2007113210(A1) 申请公布日期 2007.05.17
申请号 US20060362923 申请日期 2006.02.28
申请人 FUJITSU LIMITED 发明人 MIZUNO YUTAKA;AWAYA TOMOHARU
分类号 G06F17/50 主分类号 G06F17/50
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