发明名称 PATTERN LAYOUT AND METHOD OF GENERATING LAYOUT DATA
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a pattern layout that can prevent changes in transistor characteristics caused by rounding which generates inside a corner of a diffusive region or a gate wiring and by an alignment error of a mask. <P>SOLUTION: The pattern layout has a bend portion 13 bending into an L-shape in one side of a gate wiring 12 in a diffusive region 11 laid intersecting perpendicular to the gate wiring 12, wherein an auxiliary pattern 14 is formed in the diffusive region 11 in the other side of the gate wiring 12, the auxiliary pattern giving the same distance from the gate wiring as the distance between the bend portion 13 and the gate wiring 12. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2007121867(A) 申请公布日期 2007.05.17
申请号 JP20050316456 申请日期 2005.10.31
申请人 FUJITSU LTD 发明人 KOMAKI MASAKI
分类号 G03F1/68;G03F1/70;G06F17/50;H01L21/336;H01L21/82;H01L29/78 主分类号 G03F1/68
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