| 摘要 |
A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprises a controllable first FIFO and a controllable second FIFO. The first FIFIO is clocked by a WDQS signal and stores write data on the basis of one or more successive write commands. The second FIFO is clocked by an internal clock signal and stores, for a write operation, only addresses associated with valid write data of the write data stored in the first FIFO.
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