| 摘要 |
The present disclosure relates to a flash memory including a common source line having a predetermined width formed on a semiconductor substrate, a common source in the semiconductor substrate below the common source line, and a couple of floating gates having a predetermined width formed on both outer side walls of the common source line. The flash memory may also include a couple of tunneling oxide layers formed between the floating gate and the common source line, and between the floating gate and the semiconductor substrate, a couple of dielectric layers formed on each of the couple of floating gates, and a couple of control gates formed on each of the couple of dielectric layers. Further, the flash memory may include a couple of drains formed in the semiconductor substrate by injecting impurity ions in using the control gate and the common source line as a mask.
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