| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To suppress the increase of a clock skew on an actual device, and to strengthen on-chip dispersion resistance. <P>SOLUTION: Regions G1 to G8 comprising the prescribed number of flip flops (FF) are divided into two groups. The number of data connection paths crossing a boundary line is set to be minimum. When the boundary line crosses the data connection paths A1 and A2, the number of the data connection paths crossing the boundary line becomes 2 in minimum. Regions G1 to G4 and regions G5 to G8 are divided into groups, and clock tree synthesis (CTS) is performed. The increase of the clock skew on the actual device is suppressed and on-chip dispersion resistance can be strengthened. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
