| 摘要 |
A memory device comprising: a memory array comprising primary memory cells; at least one primary row wordline for accessing a row of said primary memory cells, said at least one primary row wordline being divided into a plurality of segments, each of which accesses a respective portion of said row of said primary memory cells; at least one row of redundant memory cells; at least one redundant row wordline for accessing said redundant memory cells, said at least one redundant row wordline being divided into a plurality of segments, each of which accesses a portion of said redundant memory cells; and a programmable logic circuit which can be selectively programmed to replace at least one of said primary row wordline segments associated with a defective memory cell with a redundant row wordline segment during memory access operation. |
