发明名称 DROPPED VOLTAGE OUTPUT CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a dropped voltage output circuit in which a latch-up phenomenon of a load circuit is prevented from start of a power source to complete start of operation of a charge pump circuit and abrupt variation of a substrate potential is prevented at the time of state shift of dropped voltage output from ON to OFF. <P>SOLUTION: This dropped voltage output circuit has a control signal input terminal, a power source voltage input terminal, a dropped voltage output terminal, and an oscillation circuit oscillating with the prescribed frequency, and the circuit also has a charge pump circuit outputting dropped power source voltage, a timer circuit setting the prescribed timer time in accordance with the prescribed frequency, a resistor of which the one end is connected to the power source voltage input terminal, a first NMOS of which the source is connected to the dropped voltage output terminal, the drain is connected to a ground potential, and the gate is connected to the other end of the resistor, and a second NMOS of which the source is connected to the dropped voltage output terminal, the drain is connected to a connection point of the first NMOS and the resistor, and the gate is connected to the output end of the timer circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p>
申请公布号 JP2006120201(A) 申请公布日期 2006.05.11
申请号 JP20040304610 申请日期 2004.10.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KOBAYASHI HIROSHI;FUJII KEIICHI;KAKUMOTO YASUNOBU;NAGASAWA TOSHINOBU
分类号 G11C11/413 主分类号 G11C11/413
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