| 摘要 |
PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which can be operated at high speed while its micro size is reduced as much as possible. SOLUTION: The nonvolatile semiconductor memory device is provided with a gate insulating layer 5, a control gate (CG) layer 6, a first silicide layer 9, a potential accumulating layer 7, a memory gate (MG) layer 8, and a second silicide layer 10. The gate insulating layer 5 is formed on the first area of a substrate 1, the CG layer 6 is formed on the gate insulating layer 5, and the first silicide layer 9 is formed on the CG layer 6, respectively. The potential accumulating layers 7 are formed on both sides of the first area of the substrate 1. The MG layer 8 is formed away from the CG layer 6 on the potential accumulating layer 7, and it includes a thick-film gate layer 8a and a thin-film gate layer 8b. The second silicide layer 10 is formed on the MG layer 8. The thick-film gate layer 8a is formed on a far side in the CG layer 6, and it is joined with the second silicide layer 10. The thin-film gate layer 8b is formed on a near side in the CG layer 6, and it is made smaller in thickness than the thick-film gate layer 8a and smaller in height than the CG layer 6. COPYRIGHT: (C)2006,JPO&NCIPI
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