| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To realize an information processor capable of changing a clock frequency division ratio waiting for timing when a glitch does not occur, in a clock frequency dividing circuit, and changing a clock without interrupting access to a memory. <P>SOLUTION: The frequency of an operation clock generated by a variable frequency divider 2 in accordance with a change in the clock frequency division ratio is changed in a clock frequency division setting register 3. At the same time, a counter circuit 6 changes the clock frequency division ratio and simultaneously counts a count number set in a clock downcount number register 7 or clock upcount number register 8. An access timing setting register 51 and a selector 52 change access timing after a counting end in the counter circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
