发明名称 |
Semiconductor device and method for fabricating the same |
摘要 |
Gate electrodes 5 A through 5 F are formed to have the same geometry, and protruding parts of the gate electrodes 5 A through 5 F extend across an isolation region onto impurity diffusion regions. The gate electrode 5 B and P-type impurity diffusion regions 7 B 6 are connected through a shared contact 9 A 1 to a first-level interconnect M 1 H, and the gate electrode 5 E and N-type impurity diffusion regions 7 A 6 are connected through a shared contact 9 A 2 to a first-level interconnect M 1 I. In this way, contact pad parts of the gate electrodes 5 A through 5 F can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.
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申请公布号 |
US2006097294(A1) |
申请公布日期 |
2006.05.11 |
申请号 |
US20050270602 |
申请日期 |
2005.11.10 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
YAMASHITA KYOJI;OTANI KATSUHIRO;ARAI KATSUYA;IKOMA DAISAKU |
分类号 |
H01L29/76;G03F1/36;G03F1/68;H01L21/28;H01L21/768;H01L21/82;H01L21/8238;H01L27/092;H01L27/118;H01L29/417 |
主分类号 |
H01L29/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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