发明名称 Bit manipulation method, apparatus and system
摘要 A bit manipulation processor, system and method are provided which reduces the number of operations performed during data processing. An additional register is used as a buffer. The buffer has a bit length which is preferably greater than the address boundaries in a memory or register address. A bitstream can be processed using the buffer by itself or in combination with a standard register, depending upon the particular function to be implemented.
申请公布号 US2006101246(A1) 申请公布日期 2006.05.11
申请号 US20040959613 申请日期 2004.10.06
申请人 IWATA EIJI 发明人 IWATA EIJI
分类号 G06F9/44 主分类号 G06F9/44
代理机构 代理人
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