发明名称 METHOD TO ENHANCE CMOS TRANSISTOR PERFORMANCE BY INDUCING STRAIN IN THE GATE AND CHANNEL
摘要 A method of manufacturing complementary metal oxide semiconductor transistors forms different types of transistors such as N-type metal oxide semiconductor (NMOS) transistors and P-type metal oxide semiconductor (PMOS) transistors (first and second type transistors) on a substrate. The method forms an optional oxide layer on the NMOS transistors and the PMOS transistors and then covers the NMOS transistors and the PMOS transistors with a hard material such as a silicon nitride layer. Following this, the method patterns portions of the silicon nitride layer, such that the silicon nitride layer remains only over the NMOS transistors. Next, the method heats the NMOS transistors and then removes the remaining portions of the silicon nitride layer. By creating compressive stress in the gates and tensile stress in the channel regions of the NMOS transistors (NFETs), without creating stress in the gates or channel regions of the PMOS transistors (PFETs), the method improves performance of the NFETs without degrading performance of the PFETs.
申请公布号 US2006099765(A1) 申请公布日期 2006.05.11
申请号 US20040904461 申请日期 2004.11.11
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 YANG HAINING S.
分类号 H01L21/336 主分类号 H01L21/336
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