发明名称 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
摘要 <p><P>PROBLEM TO BE SOLVED: To improve latch up resistance by reducing n well resistance while suppressing an increase in p well resistance, in a semiconductor device having a triple well structure. <P>SOLUTION: A plurality of n well regions 101 and a plurality of p well regions 102 are alternately formed in the substrate main surface direction, from the surface of p-type semiconductor substrate 100 to its interior. A Deep-n well region 103 is formed under the n well region 101 and p well region 102 of the p-type semiconductor substrate 100. The Deep-n well region 103 electrically connects the n well regions 101 together. At least a part of the p well regions 102 connects to a region of the p-type semiconductor substrate 100 where no Deep-n well region 103 is formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p>
申请公布号 JP2006120852(A) 申请公布日期 2006.05.11
申请号 JP20040307053 申请日期 2004.10.21
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MISAKI MAKOTO;KURIMOTO KAZUMI
分类号 H01L21/8238;H01L21/8244;H01L27/08;H01L27/092;H01L27/11 主分类号 H01L21/8238
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