发明名称 Multi chip package
摘要 A multi chip package includes a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted above the first semiconductor chip; a first bonding wire electrically coupled to a first bonding pad on the first semiconductor chip; and a second bonding wire electrically coupled to a second bonding pad on the second semiconductor chip. At least the first bonding wire is of a coated wire, which comprises a conductive core and an outer insulation coating. At least the first bonding pad is of a multi layered pad, comprising a base pad formed on the first semiconductor chip; a first conductive layer formed on the base pad; and a second conductive layer formed on the first conductive layer.
申请公布号 US2006097374(A1) 申请公布日期 2006.05.11
申请号 US20040985020 申请日期 2004.11.10
申请人 发明人 EGAWA YOSHIMI
分类号 H01L23/02 主分类号 H01L23/02
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