OUTPUT CIRCUIT FOR DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY, AND DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY

摘要

PROBLEM TO BE SOLVED: To provide a device to synchronize the output data and the data strobe signals of a double data rate (DDR) DRAM. SOLUTION: The device uses internal interleaved clock signals synchronizing with the external clocks. The delay lock loop in a DDR DRAM is locked by the external clock signals and generates internal interleaved clock signals. The internal interleaved clock signals are delay matched with the external clock signals when propagating through a timing circuit connected to latency and burst length selection signals. The data strobe signal is generated by using the clock signals from the delay-locked loop and synchronized with the internal interleaved clock signals. The data strobe signal and the data are connected through the paths having delay elements of the same number and type to provide the output data and the data strobe signal having the predetermined delay relation with the external clock signals. COPYRIGHT: (C)2006,JPO&NCIPI