发明名称 structure for semiconductor-package and manufacture method of it
摘要 PURPOSE: A method for manufacturing a semiconductor package is provided to embody a chip scale package(CSP) semiconductor package while easily stacking a plurality of semiconductor packages, by improving the structure of a lead-on-chip(LOC) package. CONSTITUTION: A method for manufacturing a semiconductor package comprises the steps of: bonding a side of a bonding part of a connecting terminal to a surface of an internal lead(2a) forming a lead frame with a bonding material; bonding a surface of a semiconductor chip to the internal lead with a bonding material when the semiconductor package is formed as a lead-on-chip(LOC) type; electrically connecting an end portion of the internal lead of the lead frame with a pad of the semiconductor chip with a wire; and sequentially molding the rest of the semiconductor chip excluding the side surface connected to an external terminal among respective bonding parts of connecting terminal, the lead frame and the wire with a molding material(4).
申请公布号 KR100578660(B1) 申请公布日期 2006.05.11
申请号 KR19990010328 申请日期 1999.03.25
申请人 发明人
分类号 H01L23/495 主分类号 H01L23/495
代理机构 代理人
主权项
地址