| 摘要 |
PROBLEM TO BE SOLVED: To uniformize bus traffic, to prevent the bus traffic from being locally increased and to effectively utilize bus bands in a system having a plurality of masters. SOLUTION: This cache memory system is provided with a multiway set associative type cache memory 20, a bus load detection part 30 for detecting the load state of a bus to which the cache memory 20 is connected and outputting bus load information D2 and a replacing way control part 40 for changing a replacing method of the cache memory 20 in accordance with the bus load information D2 outputted from the bus load detection part 30. The bus load detection part 30 is constituted of a bus load information storing part 31 for storing information corresponding to the number N1 of bus requests from a bus controller BC, a bus load determination condition setting part 32 for setting a bus load determination condition and a comparator 33 for comparing the stored value of the bus load information storing part 31 with the condition set value set by the bus load determination condition setting part 32 and outputting the compared result as bus load information. COPYRIGHT: (C)2006,JPO&NCIPI
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