发明名称 Slew rate controlled output circuit
摘要 An output circuit comprises an input node, an output node, a first output transistor, a second output transistor, a first slew rate control circuit, and a second slew rate control circuit. The first output transistor and the second output transistor are coupled in series. The first slew rate control circuit is coupled between the first output transistor and a first power supply terminal. The second slew rate control circuit is coupled between the second output transistor and a second power supply terminal. The input node is coupled to gates of the first output transistor and the second output transistor. The output node is coupled to a common node of the first output transistor and the second output transistor.
申请公布号 US2006097764(A1) 申请公布日期 2006.05.11
申请号 US20040983917 申请日期 2004.11.08
申请人 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. 发明人 YEH CHUN-YUAN
分类号 H03K5/12 主分类号 H03K5/12
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