| 摘要 |
A method and system for determining multi-thread direct memory activity is described. A pipelined circuit for tag availability with multi-threaded direct memory access activity may be employed. The pipelined circuit includes registers for providing a tag to a direct memory access (DMA) thread and receiving the tag upon completion of the DMA thread. The DMA engine is implemented in a multi-threaded environment allowing for out of order completion of the data transfer requests, such as an environment including a peripheral component interconnect extended (PCI-X) bus. The pipelined circuit provides a multi-threaded DMA engine with tags for transactions. In this manner, the number of DMA threads created and executed by the DMA engine may not exceed the number of stages in the pipelined circuit.
|
