| 摘要 |
In a memory system, a memory device that outputs a data strobe signal and memory cell data according to a read command. A memory controller receives the data strobe signal and latches the memory cell data that is output by the memory device, using an interface circuit that realigns the data strobe signal so that an edge of the data strobe signal is substantially centered on the availability of the memory cell data. The interface circuit includes a logic circuit portion that generates a plurality of selection signals in response to the read command and that outputs data strobe sampling signals in response to the selection signals, and further includes a storage portion that captures an edge of the data strobe signal in response to the data strobe sampling signals and that realigns the data strobe signal. Accordingly, the memory controller adaptively latches the data input/output signal by monitoring the data strobe signal provided by the memory device, without including a delay locked loop (DLL) circuit which has a complicated structure and consumes a large amount of power.
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