发明名称 INSPECTION APPARATUS AND METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To perform a high-speed, high-quality test by reducing inspection time for semiconductor integrated circuits under inspection (DUT). SOLUTION: An output signal of DUT1-1, DUT1-2 is converted into a DC signal which is proportional to an AC signal without amplitude loss, caused by wiring capacity or the like by an RMS/DC converter 3 provided near a buffer 2. Output data is loaded from an A/D converter 11 into a memory 12 in the test apparatus body 18 through a DUT1-1 high-speed switch 4-1, a DUT1-2 high-speed switch 4-2, and a DUT-selecting high-speed switch 4. The start and termination of the loading into the memory 12, and the control of the high-speed switches are performed comprehensively. Each output signal of the RMS/DC converter 3 is switched to a high speed to record a plurality of DC signals successively onto the memory 12. For the data loaded into the memory 12, the DC signal of each input/output signal is measured by a level measurement section 14 at an object point, is converted into amplitude by an amplitude conversion section 15, and is verified by a decision section 16 to decide the quality. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006112934(A) 申请公布日期 2006.04.27
申请号 JP20040300988 申请日期 2004.10.15
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMAKAWA SHINICHIRO
分类号 G01R31/28 主分类号 G01R31/28
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