| 摘要 |
A method and an apparatus for reducing the area and shortening the critical path of Viterbi circuits in Gigabit Ethernet systems. The present invention replaces the complex four-dimensional Euclidean distance with a simple sum of distances in each dimension as the distance criterion when a slicer is selecting the closest PAM-5 constellation point according to output voltages from an equalizer, thereby simplifying the design of Viterbi circuits.
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