Signal generation circuit for clock recovery circuit used in data recovery circuit, has two transparent latches which switch between responsive and non-responsive states depending on logic state of clock signal

摘要

A pair of serially connected latches (12,14) of the signal generation circuit (10), is switchable between responsive and non-responsive states, based on the logic state of a clock signal (CLK). The latch (12) remains in non-responsive state and the latch (14) remains in responsive state when the logic state of the clock signal is high. When the logic state of the clock signal is low, the latches switch to alternate states. Independent claims are included for the following: (1) Clock recovery circuit; (2) Verification circuit; (3) Data synchronizing circuit; and (4) Data recovery circuit.