摘要 |
<p>The present invention relates to a non-volatile memory device, comprising a memory array (10, 20) with a plurality of memory cells (100, 200) arranged in rows and columns, bit line conductors (12, 22) coupled to said rows of memory cells, an averaging circuit (11, 21) with inputs coupled to a plurality of said bit line conductors (12, 22) and being arranged to determine an average level on respective analog signal levels on said plurality of bit line conductors (12, 22), a monitoring circuit (13, 23) coupled to said averaging circuit (11, 21) and being arranged to monitor said average level and to output a refresh command when said average level shows a predetermined behaviour, and a refresh circuit (15, 25) coupled to said monitoring circuit (13, 23) and being arranged to refresh at least a selection of said plurality of memory cells (100, 200) in response to said refresh command.</p> |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V.;BLACQUIERE, JOHANNIS, F., R.;VAN ACHT, VICTOR, M., G. |
发明人 |
BLACQUIERE, JOHANNIS, F., R.;VAN ACHT, VICTOR, M., G. |