| 摘要 |
A semiconductor device includes a gate structure having a plurality of gate layers, which are layered upon a gate dielectric. A pair of thin spacers is formed on corresponding sidewalls of the gate structure. Each thin spacer is at most 25 nanometers (nm) wide. Length of the gate structure is at most 40 nm. Source and drain regions of the device are self aligned and disposed adjacently below on either side of each thin spacer and a corresponding edge of the gate structure. The source and drain regions include impurity concentrations-of a selectable type to form a smooth junction profile under each thin spacer and the corresponding edge of the gate structure.
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