发明名称 |
Data reproducing controller |
摘要 |
A data reproducing controller for operating a device for reproducing data at a high speed, which is recorded on a disc and includes an error correction code. A PI correction circuit performs an error correction process on a PI and causes a completion signal to go high whenever processing of 182 bytes of data is completed. A counter circuit sequentially increments a count value whenever the completion signal goes high. A determination circuit compares the count value with a predetermined set value and determines whether the data of which PI has undergone the error correction process is a PO row based on the comparison. The determination circuit causes a first control signal to go low when the data is a PO row. A descrambling circuit skips the data that is determined to be a PO row. |
申请公布号 |
US2006090115(A1) |
申请公布日期 |
2006.04.27 |
申请号 |
US20050296883 |
申请日期 |
2005.12.08 |
申请人 |
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发明人 |
NAGAI HIROKI;TOMISAWA SHIN-ICHIRO |
分类号 |
G06F11/10;H03M13/00;G11B20/10;G11B20/18;H03M13/29 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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