| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To suppress a current flowing at the time of reset by reducing the number of data holding circuits for writing which are reset simultaneously after finish of batch writing of data for writing of a plurality of bits, in a semiconductor memory. <P>SOLUTION: A semiconductor memory device is provided with a memory cell array 20 in which a plurality of semiconductor memory cells are arranged, a plurality of write data latch circuits 101 each having a reset function provided for holding data for writing of a plurality of bits respectively to be collectively written in a memory cell array, and a reset control circuit 200 supplying a reset signal with time division to each group in which the plurality of write data latch circuits are divided into a plurality of groups in a reset period for initializing the plurality of write data latch circuits after finish of batch writing of write data of (n) bits for the plurality of write data latch circuits. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
