| 摘要 |
The nonvolatile ferroelectric memory device having a cell array structure including sub-bitlines and main bitlines wherein a sensing voltage of sub-bitlines is transformed into a current to induce a sensing voltage of main bitlines, comprising: a plurality of cell array blocks comprising the cell array; a cell array block driver for transmitting driving signals which drive the cell array blocks into the cell array blocks; a control circuit unit for symmetrically dividing the cell array blocks and controlling data to be written in or read from the cell array blocks; and a plurality of data buses shared in the main bitlines by using switching devices and arranged vertically in both sides of the control circuit unit, wherein a layer where the driving signals lines for transmitting the driving signals into the cell array blocks are formed is positioned above a layer where the cell arrays are formed. The multi-layer structure can reduce the layout area of chips because the repeated used driving signal lines are formed above the cell arrays.
|
