发明名称 |
Faster shift value calculation using modified carry-lookahead adder |
摘要 |
Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outputs from the carry-save adder and implements an XOR operation on a most-significant bit along with its own logic operation to produce the value for the floating point multiply-accumulate operation. Modification of the carry-lookahead adder to perform the XOR operation results in elimination of an entire stage of logic.
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申请公布号 |
US7444366(B2) |
申请公布日期 |
2008.10.28 |
申请号 |
US20040853518 |
申请日期 |
2004.05.26 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;INTEL CORPORATION |
发明人 |
THAYER PAUL R.;KUMAR SANJAY |
分类号 |
G06F7/38;G06F7/50;G06F7/505;H03K19/096 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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