发明名称 Implementation of a multiplexer in integrated circuitry
摘要 A smaller, faster implementation of a multiplexer is provided. Using an improved selection encoding, the multiplexer is implemented using LUTs that may be coupled to one another using a cascade connection structure. The improved selection encoding and cascade structure allow for one-hot selection, faster routing, and more efficient use of resources.
申请公布号 US7443846(B1) 申请公布日期 2008.10.28
申请号 US20030341530 申请日期 2003.01.10
申请人 ALTERA CORPORATION 发明人 METZGEN PAUL J.
分类号 H04L12/56 主分类号 H04L12/56
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