METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

摘要

A method for manufacturing a semiconductor device is provided to minimize a step between a gate hard mask nitride layer and a dielectric by performing a CMP(Chemical Mechanical Polishing) process using slurry for a nitride layer. Plural gates(208) having a nitride layer hard mask and a junction region are formed on a silicon substrate. A first interlayer dielectric(212) being formed with an oxide layer material is formed on the silicon substrate. CMP(Chemical Mechanical Polishing) is performed on the first interlayer dielectric by using the nitride layer hard mask as a polishing stop layer. A hard mask(214) for a landing plug contact formation is formed on the resultant substrate structure on which CMP is performed. The first interlayer dielectric is etched by using the hard mask for a landing plug contact formation to form a contact hole exposing the gates and the junction region. A poly silicon layer is deposited to gap-fill the contact hole. First CMP is performed on the poly silicon layer by using a slurry for an oxide layer so that the nitride layer hard mask is exposed. Polishing speed of an oxide layer is faster than that of a nitride layer in the slurry for an oxide layer. Second CMP is performed on the poly silicon layer where the first CMP is performed by using slurry for a nitride layer. Polishing speed of a nitride layer is faster than that of the oxide layer in the slurry.