| 摘要 |
A method for fabricating a semiconductor device is provided to guarantee a leaning plug area and improve cell resistance by growing an epitaxial silicon layer on an active region and an isolation layer of a predetermined width in forming a recess gate so that the area of the minor axis direction of the active region is expanded. A gate polysilicon layer pattern is formed on a semiconductor substrate including an isolation layer(14) for defining a first active region(12a). A light oxidation process can be performed to form a light oxide layer(22) on the sidewall of the gate polysilicon layer pattern. A first spacer is formed on the upper surface and sidewall of the gate polysilicon layer pattern. A second active region(12b) is formed on the first active region and a predetermined width of the isolation layer in the minor axis direction of the first active region. A planarization process is performed on the first spacer to expose the gate polysilicon layer. A gate electrode layer pattern(28) and a gate hard mask layer pattern(30) are formed on the gate polysilicon layer pattern to complete a gate.
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