| 摘要 |
A memory device capable of inputting or outputting plural data concurrently is provided to input or output the data one between a pair of global bit lines via access control of a controller though not using other special switch on the global bit line. A memory device includes plural basic cell blocks(10_1-10_N), global sense amplifiers(14,14_1), and global bit lines(R_GBL,L_GBL). The global sense amplifiers latch plural data which is accessed by each unit cell. The global bit lines transmit data among the global sense amplifiers and the basic cell blocks. The basic cell block includes a unit cell block(11), the first bit line sense amplifier(12), the second bit line sense amplifier(12_1), the first controller(13) and the second controller(13_1). The unit cell block has plural unit cells. The first bit line sense amplifier, installed at one side of the unit cell block, senses partial data of the unit cell block and amplifies the sensed partial data. The second bit line sense amplifier, installed at the other side of the unit cell block, senses remaining data of the unit cell block and amplifies the sensed remaining data. The first controller, installed at one side of the first bit line sense amplifier, performs a control operation for generating a compensation signal of data inputted via the right global bit line in a write access mode, writing data to the unit cell block, and outputting the data of the unit cell block via the right global bit line in a read access mode. The second controller, installed at one side of the second bit line sense amplifier, performs a control operation for generating a compensation signal of data inputted via the left global bit line in a write access mode, writing data to the unit cell block, and outputting the data of the unit cell block via the left global bit line in a read access mode.
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