INNER CLOCK GENERATOR IN A SYSTEM AND INNER CLOCK GENERATING METHOD THEREOF

摘要

An internal clock generator of a system and a method thereof are provided to prevent a skew between data and clocks, which get different according to driving power levels, even though the driving power level get lower. A method of an internal clock generator includes the following several steps. A power sensor of an internal power generator senses a voltage level of a driving voltage(S110). The power sensor determines whether the sensed voltage level is higher than a voltage level of a target voltage, and output a sensed signal according to a determining result(S120). If the sensed voltage level of the driving voltage is higher than that of the target voltage, the internal clock generator generates a normal clock(S130). Otherwise, the internal clock generator generates an abnormal clock(S135). A system performs an operation in synchronization with the internal clock selected by a selector(S140).