发明名称 TEST CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a test circuit in which a test time can be reduced, thereby, a test cost can be reduced. SOLUTION: An address generating circuit 105 generates a test address 107 synchronizing with an external clock 115, and supplies this to a ROM 101 as a ROM address 104. A MISR 112 compresses output ROM data 106 output from the ROM 101 corresponding to input ROM address 104. A 4 bits shift register 114 outputs compressed data (MISR output 113), outputting all collected 4 data. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008159149(A) 申请公布日期 2008.07.10
申请号 JP20060346206 申请日期 2006.12.22
申请人 OKI ELECTRIC IND CO LTD 发明人 YUSA ATSUSHI
分类号 G11C29/12;G01R31/28;G11C29/40 主分类号 G11C29/12
代理机构 代理人
主权项
地址