| 摘要 |
<p>An electrically programmable memory cell and corresponding method for fabricating the same, provide a reduced electron tunneling threshold to reduce parasitic substrate currents during cell programming. A floating gate (310) of the cell is formed over an injector dopant region (255; 440) diffused within and encompassed by a first dopant region (245; 415). Both dopant regions are situated beneath a self -aligned tunneling window (240; 410) of the floating gate. The dopant regions are each high concentration dopants (BN+, P+; 420, 435) and of complementary species to one another. The injector dopant region produces an increase in surface potential (??<SUB>s</SUB>) that lowers a tunneling barrier height and produces the lower electron tunneling threshold.</p> |
